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quad, 16 - /12 - bit nanodac+ with i 2 c interface data sheet ad5696 / ad5694 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012 C 2013 analog d evices, inc. all rights reserved. technical support www.analog.com features high relative accuracy (inl): 2 lsb maximum at 1 6 bits tiny package : 3 mm 3 mm , 16 - lead lfcsp total unadjusted error (tue): 0.1% of fsr maximum offset error: 1.5 mv maximum gain error: 0.1% of fsr maximum high drive capability: 20 ma , 0.5 v from supply rails user - selectable gain of 1 or 2 (gain pin) reset to zero scale or midscale (rstsel pin) 1.8 v logic compatibility 400 khz i 2 c - compat i ble serial interface 4 i 2 c addresses available low glitch: 0.5 nv - sec robust 3.5 kv hbm and 1.5 kv ficdm esd rating low power: 1 . 8 mw at 3 v 2.7 v to 5.5 v power supply ?40c to +105c temperature range applications digital gain and offset adjustment programmable attenuato rs process control (plc i/o cards) industrial a utomation data acquisition systems functional block dia gram figure 1. general description the ad5696 and ad5694 , members of the nano dac+? family, are low power, quad, 1 6 - /12 - bit buffered voltage out put dac s. the device s include a gain select pin giving a full - sc ale output of 2.5 v ( gain = 1) or 5 v ( gain = 2). the device s operate from a single 2.7 v to 5.5 v supply, are guaranteed monotonic by design , and exhibi t less than 0.1% fsr gain error and 1.5 mv offset error performance. the device s are available in a 3 mm 3 mm lfcsp package and in a tssop package. the ad5696 / ad5694 incorporate a power - on reset circuit and a rstsel pin ; the rstsel pin ensures that the dac outputs power up to zero scale or midscale and remain at that level until a valid write takes place. the part s contain a per - channel power - down feature that reduces the current consumption of the device in power - down mode to 4 a at 3 v. the ad5696 / ad5694 use a versatile 2 - wire serial interface that operates at clock rates up to 400 khz and include a v logic pin intended for 1.8 v/3 v/5 v logic. table 1 . quad nano dac+ devices interface reference 16 - bit 14 - bit 12 - bit spi internal ad5686r ad5685r ad5684r external ad5686 ad5684 i 2 c internal ad5696r ad5695r AD5694R external ad5696 ad5694 product highlights 1. high relative accuracy (inl) . ad5696 (16 - bit): 2 lsb maximum ad5694 (12 - bit): 1 lsb maximum 2. excellent dc performance . total unadjusted error: 0.1% of fsr maximum offset error: 1.5 mv maximum gain error: 0.1% of fsr maximum 3. two package options. 3 mm 3 mm , 16 - lead lfcsp 16- lead tssop scl v logic sda a1 a0 input register dac register string dac a buffer v out a input register dac register string dac b buffer v out b input register dac register string dac c buffer v out c input register dac register string dac d buffer v out d v ref gnd v dd power- down logic power-on reset gain = 1/2 interface logic rstsel gain ldac reset ad5696/ad5694 10799-001
ad5696/ad5694 data sheet rev. a | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product hi ghlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac characteristics ........................................................................ 5 timing characteristics ................................................................ 6 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 esd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 typical performance characteristics ............................................. 9 terminology .................................................................................... 14 theory of operation ...................................................................... 16 digital - to - analog converter .................................................... 16 transfer function ....................................................................... 16 dac architecture ....................................................................... 16 serial interface ............................................................................ 17 write and up date commands .................................................. 18 i 2 c slave address ........................................................................ 18 serial operation ......................................................................... 18 write operation .......................................................................... 18 read operati on ........................................................................... 19 multiple dac readback sequence .......................................... 19 power - down operation ............................................................ 20 load dac (hardware ldac pin) ........................................... 20 ldac mask register ................................................................. 21 hardware reset pin ( reset ) ................................................... 21 reset select pin (rstsel) ........................................................ 21 applications information .............................................................. 22 microprocessor interfacing ....................................................... 22 ad5696/ad5694 to adsp - bf531 interface .......................... 22 layout guidelines ....................................................................... 22 galvanical ly isolated interface ................................................. 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 24 revision history 6/13 rev. 0 to rev. a changes to pin gain and pin rstsel descriptions; table 7 ....... 8 7 /12 revision 0: initial version
data sheet ad5696/ad5694 rev. a | page 3 of 24 specifications v dd = 2.7 v to 5.5 v; v ref = 2 .5 v; 1.8 v v logic 5 .5 v; r l = 2 k? ; c l = 200 pf; all specifications t min to t max , unless otherwise noted. table 2 . a grade b grade parameter min typ max min typ max unit test conditions/comments 1 static performance 2 ad5696 resolution 16 16 bits relative accuracy 2 8 1 2 lsb gain = 2 2 8 1 3 lsb gain = 1 differential nonlinearity 1 1 lsb guaranteed monotonic by design ad5694 resolution 12 12 bits relative accuracy 0.12 2 0.12 1 lsb differential nonlinearity 1 1 lsb guaranteed monotonic by design zero - code error 0.4 4 0.4 1.5 mv all 0s loaded to dac register offset error +0.1 4 +0.1 1.5 mv full - scale error +0.01 0.2 +0.01 0.1 % of fsr all 1s loaded to dac register gain error 0.02 0.2 0.02 0.1 % of fsr total unadjusted error 0.01 0.25 0.01 0.1 % of fsr g ain = 2 0.2 5 0.2 % of fsr g ain = 1 offset error drift 3 1 1 v/c gain temperature coefficient 3 1 1 ppm of fsr/c dc power supply rejection ratio 3 0.15 0.15 mv/v dac code = midscale; v dd = 5 v 10 % dc crosstalk 3 2 2 v due to single channel, full - scale output change 3 3 v/ma due to load current change 2 2 v due to power - down (per channel) output characteristics 3 output voltage range 0 v ref 0 v ref v gain = 1 0 2 v ref 0 2 v ref v gain = 2 (see figure 20) capacitive load stability 2 2 nf r l = 10 10 nf r l = 1 k? resistive load 4 1 1 k? load regulation dac code = midscale 80 80 v/ma 5 v 10%; ?30 ma i out +30 ma 80 80 v/ma 3 v 10%; ?20 ma i out + 20 ma short - circuit current 5 40 40 ma load impedance at rails 6 25 25 ? see figure 20 power - up time 2.5 2.5 s coming out of power - down mode; v dd = 5 v reference input reference current 9 0 9 0 a v ref = v dd = 5.5 v, gain = 1 180 180 a v ref = v dd = 5.5 v, gain = 2 reference input range 1 v dd 1 v dd v gain = 1 1 v dd /2 1 v dd /2 v gain = 2 reference input impedance 16 16 k? gain = 2 32 32 k? gain = 1
ad5696/ad5694 data sheet rev. a | page 4 of 24 a grade b grade parameter min typ max min typ max unit test conditions/comments 1 logic inputs 3 input current 2 2 a per pin input low voltage, v inl 0.3 v logic 0.3 v logic v input high voltage, v inh 0.7 v logic 0.7 v logic v pin capacitance 2 2 pf logic outputs (sda) 3 output low voltage, v ol 0.4 0.4 v i sink = 3 ma output high voltage, v oh v logic ? 0.4 v logic ? 0.4 v i source = 3 ma floating state output capacitance 4 4 pf power requirements v logic 1.8 5.5 1.8 5.5 v i logic 3 3 a v dd 2.7 5.5 2.7 5.5 v gain = 1 v ref + 1.5 5.5 v ref + 1.5 5.5 v gain = 2 i dd v ih = v dd , v il = gnd, v dd = 2.7 v to 5.5 v normal mode 7 0.59 0.7 0.59 0.7 ma all power - down modes 8 1 4 1 4 a ?40c to +85c 6 6 a ?40c to +105c 1 temperature range is ?40c to + 105c. 2 dc specifications are tested with the outputs unloaded, unless otherwise noted. upper dead band (10 mv) exists only when v ref = v dd with gain = 1 or when v ref /2 = v dd with gain = 2. linearity calculated using a reduced code range of 256 to 65,280 ( ad5696 ) or 12 to 4080 ( ad5694 ). 3 guaranteed by d esign and characterization; not production tested. 4 channel a and channel b can have a combined output current of up to 30 ma. similarly, channel c and channel d can have a comb ined output current of up to 30 ma up to a junction temperature of 110c. 5 v d d = 5 v . the device includes current limiting that is intended to protect the device during tempor ary overload conditions. junction temperature can be exc e e d ed during current limit. operation above the specified max imum junction temperature may impair device reliability. 6 when drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 typical channel resistance of the output devices. for example , when sinking 1 m a , the minimum output voltage = 25 ? 1 ma = 25 mv ( see figure 20) . 7 interface inactive. all dacs active. dac outputs unloaded. 8 all dacs powered down.
data sheet ad5696/ad5694 rev. a | page 5 of 24 ac characteristics v dd = 2.7 v to 5.5 v; v ref = 2 .5 v; 1.8 v v logic 5.5 v; r l = 2 k? ; c l = 200 pf; all specifications t min to t max , unless otherwise noted. table 3 . parameter 1 , 2 min typ max unit test conditions/comments 3 output voltage settling time ? to ? scale settling to 2 lsb ad5696 5 8 s ad5694 5 7 s slew rate 0.8 v/s digital -to - analog glitch impulse 0. 5 nv - sec 1 lsb change around major carry transition digital feedthrough 0.1 3 nv - sec multiplying bandwidth 500 khz digital crosstalk 0.1 nv - sec analog crosstalk 0.2 nv - sec dac -to - dac crosstalk 0.3 nv - s ec total harmonic distortion 4 ?80 db at t a , bw = 20 khz, v dd = 5 v, f out = 1 khz output noise spectral density 1 00 nv/ hz dac code = midscale, 10 khz , gain = 2 output noise 6 v p -p 0.1 hz to 10 hz signal - to - noise ratio ( snr ) 90 db at t a , bw = 20 khz, v dd = 5 v, f out = 1 khz spurious - free dynamic range ( sfdr ) 83 db at t a , bw = 20 khz, v dd = 5 v, f out = 1 khz signal - to - noise - and - distortion ratio ( sinad ) 80 db at t a , bw = 20 khz, v dd = 5 v, f out = 1 khz 1 guaranteed by design and characterization; not production tested. 2 see the terminology s ection. 3 temperature range is ?40c to +105c; typical at 25c. 4 digitally generated sine wave at 1 khz.
ad5696/ad5694 data sheet rev. a | page 6 of 24 timing characteristics v dd = 2.7 v to 5.5 v; 1.8 v v logic 5.5 v; all specifications t min to t max , unless otherwise noted. table 4. parameter 1, 2 min max unit description t 1 2.5 s scl cycle time t 2 0.6 s t high , scl high time t 3 1.3 s t low , scl low time t 4 0.6 s t hd,sta , start/repeated start hold time t 5 100 ns t su,dat , data setup time t 6 3 0 0.9 s t hd,dat , data hold time t 7 0.6 s t su,sta , repeated start setup time t 8 0.6 s t su,sto , stop condition setup time t 9 1.3 s t buf , bus free time between a stop condition and a start condition t 10 4 0 300 ns t r , rise time of scl and sda when receiving t 11 4, 5 20 + 0.1c b 300 ns t f , fall time of scl and sda when transmitting/receiving t 12 20 ns ldac pulse width t 13 400 ns scl rising edge to ldac rising edge t sp 6 0 50 ns pulse width of suppressed spike c b 5 400 pf capacitive load for each bus line 1 see figure 2. 2 guaranteed by design and characterization; not production tested. 3 a master device must provide a hold time of at least 300 ns for the sda signal (ref erred to the v ih min of the scl signal) to bridge the undefined region of the scl falling edge. 4 t r and t f are measured from 0.3 v dd to 0.7 v dd . 5 c b is the total capacitance of one bus line in pf. 6 input filtering on the scl and sda inputs suppresses noise spikes that are less than 50 ns. timing diagram figure 2. 2-wire serial interface timing diagram scl sda t 1 t 3 ldac 1 ldac 2 start condition repeated start condition stop condition notes 1 asynchronous ldac update mode. 2 synchronous ldac update mode. t 4 t 6 t 5 t 7 t 8 t 2 t 13 t 4 t 11 t 10 t 12 t 12 t 9 10799-002
data sheet ad5696/ad5694 rev. a | page 7 of 24 absolute maximum rat ings t a = 25c, unless otherwise noted. table 5 . parameter rating v dd to gnd ?0.3 v to +7 v v logic to gnd ?0.3 v to +7 v v out to gnd ?0.3 v to v dd + 0.3 v v ref to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd 1 ?0.3 v to v logic + 0.3 v sda and scl to gnd ?0.3 v to +7 v operating temperature range ?40c to +105c storage temperature range ?65c to +150c junction temperature 125c reflow soldering peak temperature, pb free (j - std - 020) 260c esd human body model (hbm) 3.5 kv field - induced charged device model ( ficdm ) 1.5 kv 1 excluding sda and scl. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those ind icated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. this value was measured using a jedec standard 4 - layer board with zero airflow . for the lfcsp package, the exposed pad must be tied to gnd. table 6 . thermal resistance package type ja unit 16 - lead lfcsp 70 c/w 16 - lead tssop 112.6 c/w esd caution
ad5696/ad5694 data sheet rev. a | page 8 of 24 pin configuration s and function descrip tions figure 3. pin configuration , 16 - lead lfcsp figure 4. pin configuration , 16 - lead tssop table 7 . pin function descriptions pin no. mnemonic description lfcsp tssop 1 3 v out a analog output voltage from dac a. the output amplifier has rail -to - rail operation. 2 4 gnd ground reference point for all circuitry on the part. 3 5 v dd power supply input. the part s can be operated from 2.7 v to 5.5 v . the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 4 6 v out c analog output voltage from dac c. the output amplifier has rail -to - rail operation. 5 7 v out d analog output voltage from dac d. the output amplifier has rail -to - rail operation. 6 8 sd a serial data input. this pin is used in conjunction with the scl line to clock data into or out of the 24 - bit input shift register. sda is a bidirectional, open - drain data line that should be pulled to the supply with an external pull - up resistor. 7 9 ldac ldac can be operated in two modes, asynchronous update mode and synchronous update mode . pulsing this pin low allows any or all dac re gisters to be updated if the input registers have new data ; a ll dac outputs are simultaneously update d . this pin can also be tied permanently low. 8 10 gain g ain select pin. when this pin is tied to gnd , all four dac outputs have a span of 0 v to v ref . when this pin is tied to v logic , all four dac outputs have a span of 0 v to 2 v ref . 9 11 v logic digital power supply. voltage ranges from 1.8 v to 5.5 v. 10 12 a0 address input. sets the first lsb of the 7 - bit slave address. 11 13 scl serial c lock line. this pin is used in conjunction with the sda line to clock data into or out of the 24 - bit input shift register. 12 14 a1 address input. sets the second lsb of the 7 - bit slave address. 13 15 reset asynchronous reset input. the reset input is falling edge sensitive. when reset is activated (low) , the input register and the dac register are updated with zero scale or midscale, depending on the state of the rstsel pin. when reset is low, all ldac pulses are ignored. 14 16 rstsel power - on reset pin. when this pin is tied to gnd, all four dacs are power ed up to zero scale. when this pin is tied to v logic , all four dacs are power ed up to midscale. 15 1 v ref reference input voltage. 16 2 v out b analog output voltage from dac b. the output amplifier has rail -to - rail operation. 17 n/a epad exposed pad . the exposed pad must be tied to gnd. 12 11 10 1 3 4 a1 scl a0 9 v logic v out a v dd 2 gnd v out c 6 sda 5 v out d 7 ldac 8 gain 16 v out b 15 v ref 14 rstsel 13 reset ad5696/ad5694 notes 1. the exposed pad must be tied to gnd. top view (not to scale) 10799-006 1 2 3 4 5 6 7 8 v out b v out a gnd v out d v out c v dd v ref sda 16 15 14 13 12 11 10 9 reset a1 scl gain ldac v logic a0 rstsel top view (not to scale) ad5696/ ad5694 10799-007
data sheet ad5696/ad5694 rev. a | page 9 of 24 typical performance characteristi cs figure 5. ad5696 inl figure 6. ad5694 inl figure 7. ad5696 dnl figure 8. ad5694 dnl figure 9 . inl error and dnl error vs. temperature figure 10 . inl error and dnl error vs. v ref 10 ?10 ?8 ?6 ?4 ?2 0 2 4 8 6 0 10000 20000 30000 40000 50000 60000 inl (lsb) code v dd = 5v t a = 25c reference = 2.5v 10799- 1 18 10 ?10 ?8 ?6 ?4 ?2 0 2 4 8 6 0 625 1250 1875 2500 3125 3750 4096 inl (lsb) code v dd = 5v t a = 25c reference = 2.5v 10799-120 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.8 0.6 0 10000 20000 30000 40000 50000 60000 dnl (lsb) code v dd = 5v t a = 25c reference = 2.5v 10799-121 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.8 0.6 0 625 1250 1875 2500 3125 3750 4096 dnl (lsb) code v dd = 5v t a = 25c reference = 2.5v 10799-123 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 ?40 110 60 10 error (lsb) temperature (c) inl dnl v dd = 5v t a = 25c reference = 2.5v 10799-124 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 error (lsb) v ref (v) inl dnl v dd = 5v t a = 25c 10799-125
ad5696/ad5694 data sheet rev. a | page 10 of 24 figure 11 . inl error and dnl error vs. supply voltage figure 12 . gain error and full - scale error vs. temperature figure 13 . zero - code error and offset error vs. temperature figure 14 . gain error and full - scale error vs. supply voltage figure 15 . zero - code error and offset error vs. supply voltage figure 16 . tue vs. temperature 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 2.7 5.2 4.7 4.2 3.7 3.2 error (lsb) supply voltage (v) inl dnl v dd = 5v t a = 25c reference = 2.5v 10799-126 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 ?40 ?20 0 20 40 60 80 100 120 error (% of fsr) temperature (c) gain error full-scale error v dd = 5v t a = 25c reference = 2.5v 10799-127 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?40 ?20 0 20 40 60 80 100 120 error (mv) temperature (c) offset error zero-code error v dd = 5v t a = 25c reference = 2.5v 10799-128 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 2.7 5.2 4.7 4.2 3.7 3.2 error (% of fsr) supply voltage (v) gain error full-scale error v dd = 5v t a = 25c reference = 2.5v 10799-129 1.5 ?1.5 ?1.0 ?0.5 0 0.5 1.0 2.7 5.2 4.7 4.2 3.7 3.2 error (mv) supply voltage (v) zero-code error offset error v dd = 5v t a = 25c reference = 2.5v 10799-130 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 ?40 ?20 0 20 40 60 80 100 120 total unadjusted error (% of fsr) temperature (c) v dd = 5v t a = 25c reference = 2.5v 10799-131
data sheet ad5696/ad5694 rev. a | page 11 of 24 figure 17 . tue vs. supply voltage , gain = 1 figure 18 . tue vs. code , ad5696 figure 19 . i dd histogram at 5 v figure 20 . headroom/footroom vs. load current figure 21 . source and sink capability at 5 v figure 22 . source and sink capability at 3 v 0.10 0.08 0.06 0.04 0.02 0 ?0.02 ?0.04 ?0.06 ?0.08 ?0.10 2.7 5.2 4.7 4.2 3.7 3.2 total unadjusted error (% of fsr) supply voltage (v) v dd = 5v t a = 25c reference = 2.5v 10799-132 0 ?0.01 ?0.02 ?0.03 ?0.04 ?0.05 ?0.06 ?0.07 ?0.08 ?0.09 ?0.10 0 10000 20000 30000 40000 50000 60000 65535 total unadjusted error (% of fsr) code v dd = 5v t a = 25c reference = 2.5v 10799-133 25 20 15 10 5 0 540 560 580 600 620 640 hits i dd (ma) v dd = 5v t a = 25c reference = 2.5v 10799-135 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 5 10 15 20 25 30 v out (v) load current (ma) sourcing, 2.7v sourcing, 5v sinking, 2.7v sinking, 5v 10799-200 7 ?2 ?1 0 1 2 3 4 5 6 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v out (v) load current (a) 0xffff 0x4000 0x8000 0xc000 0x0000 v dd = 5v t a = 25c reference = 2.5v gain = 2 10799-138 5 ?2 ?1 0 1 2 3 4 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v out (v) load current (a) 0xffff 0x4000 0x8000 0xc000 0x0000 v dd = 3v t a = 25c reference = 2.5v gain = 1 10799-139
ad5696/ad5694 data sheet rev. a | page 12 of 24 figure 23 . supply current vs. temperature figure 24 . settling time figure 25 . power - on reset to 0 v figure 26 . exiting power - down to midscale figure 27 . digital - to- analog glitch impulse figure 28 . analog crosstalk, v out a 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ?40 110 60 10 current (ma) temperature (c) full-scale 10799-140 0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 10 320 160 40 80 20 v out (v) time (s) v out a v out b v out c v out d v dd = 5v t a = 25c reference = 2.5v ? to ? scale 10799-141 ?0.01 0 0.06 0.01 0.02 0.03 0.04 0.05 ?1 0 6 1 2 3 4 5 ?10 15 10 0 5 ?5 v out (v) v dd (v) time (s) v out d v dd v out a v out b v out c t a = 25c reference = 2.5v 10799-142 0 1 3 2 ?5 10 0 5 v out (v) time (s) v out d v out a v out b v out c v dd = 5v t a = 25c reference = 2.5v gain = 1 gain = 2 10799-143 2.4988 2.5008 2.5003 2.4998 2.4993 0 12 8 10 4 6 2 v out (v) time (s) channel b t a = 25c v dd = 5.25v reference = 2.5v code = 0x7fff to 0x8000 energy = 0.227206nv-sec 10799-144 ?0.002 ?0.001 0 0.001 0.002 0.003 0 25 20 10 15 5 v out ac-coupled (v) time (s) v out b v out c v out d 10799-145
data sheet ad5696/ad5694 rev. a | page 13 of 24 figure 29 . 0.1 hz to 10 hz output noise plot figure 30 . total harmonic distortion at 1 khz figure 31 . settling time vs. capacitive load figure 32 . multiplying bandwidth ch1 10v m1.0s a ch1 802mv 1 t v dd = 5v t a = 25c reference = 2.5v 10799-146 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0 20000 16000 8000 12000 4000 2000 18000 10000 14000 6000 thd (dbv) frequency (hz) v dd = 5v t a = 25c reference = 2.5v 10799-149 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 1.590 1.630 1.620 1.600 1.610 1.625 1.605 1.615 1.595 v out (v) time (ms) 0nf 0.1nf 10nf 0.22nf 4.7nf v dd = 5v t a = 25c reference = 2.5v 10799-150 ?60 ?50 ?40 ?30 ?20 ?10 0 10k 10m 1m 100k bandwidth (db) frequency (hz) v dd = 5v t a = 25c reference = 2.5v, 0.1v p-p 10799-151
ad5696/ad5694 data sheet rev. a | page 14 of 24 terminology relative accuracy or integral nonlinearity (inl) r elative accuracy or integral nonlinearity is a measurement of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. figure 5 and figure 6 show typical inl vs. code plots. differential nonlinearity (dnl) differential nonlinearit y is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. t he ad5696 / ad5694 are guaranteed monotonic by design. figure 7 and figure 8 show typical dnl vs. code plots. zero - code error zero - code error is a measurement of the output error when zero code (0x0000) is loaded to the dac register. ideally, the output should be 0 v. the zero - code error is always positive in the ad5696 / ad5694 because the output of the dac cannot go below 0 v due to a combination of the offset errors in the dac and the output amplifier. zero - code error is expressed in mv. figure 13 shows a plot of zero - code error vs. temperature. full - scale error full - scale error is a measurement of the output error when full - scale code (0xffff) is loaded to the dac register. ideally, the output should be v dd ? 1 lsb. full - scale error is expressed as a percent age of the full - scale range (% of fsr). figure 12 shows a plot of f ull - scale error vs. temperature. gain error gain error is a measurement of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal expressed in % of fsr. gain temperature coeffic ient gain temperature coefficient is a measurement of the change in gain error with changes in temperature. it is expressed in ppm of fsr/c. offset error offset error is a measur ement of the difference between v out (actual) and v out (ideal) expressed in mv in the linear region of the transfer function. it can be negative or p ositive. offset error drift offset error drift is a measurement of the change in offset error with change s in temperature. it is expressed in v/c. dc power supply rejection ratio (psrr) dc psrr indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for mid scale output of t he dac. it is mea - sured in mv/v . v ref is held at 2 .5 v, a n d v dd is varied by 10%. output voltage settling time th e output voltage settling time is the amount of time it takes for the output of a dac to settle to a specified level for a ? to ? full - scale input ch ange . digital -to - analog glitch impulse digital - to - analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv - s ec and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000) (see figure 27 ). digital feedthrough digital feedthrough is a measure ment of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv - s ec and measured with a full - scale code change on the data bus, that is, from all 0s to all 1s and vice versa. noise spectral density (nsd) noise spectral density is a measurement of the internally gener - ate d random noise. random noise is characterized as a spectral density (nv/hz) and is measured by loading the dac to mid - scale and measuring noise at the output. it is measured in nv/hz. dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full - scale output change on one dac (or soft power - down and power - up) while monitoring another dac kept at midscale. it is expressed in v. dc crosstalk due to load current change is a measurement of the impact that a change in load current on one dac has on another dac kept at midscale. it is expressed in v/ma. digital crosstalk digital crosstalk is the glitch impulse transferred to the ou tput of one dac at midscale in response to a full - scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is expressed in nv - s ec . analog crosstalk analog crosstalk is the glitch impulse transferred to the output of one dac in response to a change in the output of another dac. to measure analog crosstalk, load one of the input registers with a full - scale code change (all 0s to all 1s and vice versa) , and then execute a software ldac and monitor the output of the dac whose digital code was not changed. the area of the glitch is expressed in nv - s ec .
data sheet ad5696/ad5694 rev. a | page 15 of 24 dac -to - dac crosstalk dac - to - dac crosstalk is the glitch impulse transferred to the output of one dac in response to a digital code change and subsequent analog output change of another dac. it is measured by loading one channel with a full - scale code change (all 0s to all 1s and vice versa) using the write to and update commands while monitoring the output of another channel that is at mid - scale. the energy of the glitc h is expressed in nv - s ec . multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full - scale code loaded to the dac) appears on the output. the multiply ing bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) thd is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac ; thd is a measurement of the harmonics present on the dac output. it is measured in db.
ad5696/ad5694 data sheet rev. a | page 16 of 24 theory of operation digital - to - analog converter t he ad5696 / ad5694 are quad , 1 6 - /12 - bit, serial input, voltage output dac s that operate from supply voltages of 2.7 v to 5.5 v. data is written to the ad5696 / ad5694 i n a 2 4 - bit word format via a 2 - wire serial interface. t h e ad5696 / ad5694 incorporate a power - on reset circuit to ensure that the dac output powers up to a known output state. the device s also ha ve a software power - down mode that reduces the current consumption to 4 a . transfer function because the input coding to the dac is straight binary, the ideal output voltage is given by ? ? ? ? ? ? = n ref out d gain v v 2 where: v ref is the value of the external reference. gain is the gain o f the output amplifier and is set to 1 by default. the gain can be set to 1 or 2 using the gain select pin. when the gain pin is tied to gnd, all four dac outputs have a span of 0 v to v ref . when this pin is tied to v dd , all four dac outputs have a span of 0 v to 2 v ref . d is the decimal equivalent of the binary code that is loaded to the dac register as follows: 0 to 4095 for the 12 - bit ad5694 , and 0 to 65,535 for the 16 - bit ad5696 . n is the dac resolution ( 12 bits or 16 bits) . dac architecture the dac architecture consists of a string dac followed by an output amplifier. figure 33 shows a block diagram of the dac architecture. figure 33 . single dac channel architecture block diagram the resistor string structure is shown in figure 34. each resistor in the string has a v alue r. the code loaded to the dac register determines the node on the string from which the voltage is tapped off and fed into the output amplifier. the voltage is tapped off by closing one of the switches that connect the string to the amplifier. because the ad5696 / ad5694 are a string of re sistors, they are guaranteed monotonic. figure 34 . resistor string structure output amplifiers the output buffer amplifier can generate rail - to - rail voltages on its output for an output range of 0 v to v dd . the actual range depends on the value of v ref , the gain pin, the offset error , and the gain error. the gain pin selects the gain of the output . ? when this pin is tied to gnd , all four output s have a gain of 1 , and the output range is from 0 v to v ref . ? when this pin is tied to v dd , all four output s have a gain of 2 , and the output range is from 0 v to 2 v ref . the output amplifiers are capable of driving a load of 1 k? in parallel with 2 n f to gnd . the slew rate is 0.8 v/s with a ? to ? scale settling time of 5 s. input register dac register resistor string ref (+) v ref gnd ref (?) v out x gain (gain = 1 or 2) 10799-052 r r r r r to output amplifier v ref 10799-053
data sheet ad5696/ad5694 rev. a | page 17 of 24 seria l interface t he ad5696 / ad5694 have a 2 - wire , i 2 c - compatible serial interface ( see the i 2 c - bus specification , version 2.1, january 2000, available from philips semiconductor) . see figure 2 for a timing diagram of a typi cal write sequence. the ad5696 / ad5694 can be connected to an i 2 c bus as slave device s , under the control of a master device . the ad5696 / ad5694 support sta ndard (100 khz) and fast (400 khz) data transfer modes. support is not provided for 10 - bit addressing or general call addressing. input shift register the input shift register of the ad5696 / ad5694 is 2 4 bits wide. data is loaded into the device , msb first , as a 24 - bit word under the control of the serial clock input, scl. the first eight msbs make up the command byte (see figure 35 and figure 36) . ? the first four bits of the command byte are the command bits (c3, c2, c1, and c0), which control the mode of oper - ation of the device ( see table 8 ) . ? the last four bits of the command byte are the address bits ( dac d , dac c , dac b , and dac a ) , which select the dac that is operated on by the command (s ee table 9 ). the 8 - bit command byte is followed by two data bytes, which contain the data - word. for the ad5696 , t he data - word comprises the 1 6 - bit input code (see figure 35 ); for the ad5694 , the data - word comprises the 12 - bit input code followed by four dont care bits (see figure 36 ). the data bits are transferred to the input shift register on the 24 falling edge s of scl. commands can be executed on one dac channel, any two or three dac channels, or on all four dac channels, depending on the address bits selected (see table 9 ). table 8 . command definitions co mmand bits c3 c2 c1 c0 command 0 0 0 0 no operation 0 0 0 1 write to input register n ( d ependent on ldac ) 0 0 1 0 update dac register n with contents of input register n 0 0 1 1 wr ite to and update dac channel n 0 1 0 0 power down/power up dac 0 1 0 1 hardware ldac mask register 0 1 1 0 software r eset (power - on reset) 0 1 1 1 reserved 1 x 1 x 1 x 1 reserved 1 x = dont care. table 9 . address bits and selected dacs address bits selected dac channel s 1 dac d dac c dac b dac a 0 0 0 1 dac a 0 0 1 0 dac b 0 0 1 1 dac a and dac b 0 1 0 0 dac c 0 1 0 1 dac a and dac c 0 1 1 0 dac b and dac c 0 1 1 1 dac a, dac b, and dac c 1 0 0 0 dac d 1 0 0 1 dac a and dac d 1 1 1 1 all dacs 1 any combination of dac channels can be selected using the address bits. figure 35 . input shift register content s, ad5696 figure 36 . input shift register content s, ad5694 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c3 c2 c1 c0 dac d dac c dac b dac a d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 command dac address dac data dac data command byte data high byte data low byte 10799-302 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c3 c2 c1 c0 dac d dac c dac b dac a d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x command dac address dac data dac data command byte data high byte data low byte 10799-300
ad5696/ad5694 data sheet rev. a | page 18 of 24 write and update com mands for more information about the ldac function, see the load dac (hardware ldac pin) section. write to input register n (dependent on ldac ) command 0001 allows the user to write to each dac s dedicated input register individually. when ldac is low, the input register is transparent (if not controlled by the ldac mask register). update dac register n with contents of input register n command 0010 loads the dac registers/outputs with the contents of the input registers selected by the address bits (see table 9 ) and update s the dac outputs directly. write to and update dac channel n (independent of ldac ) command 0011 allows the user to write to the dac registers and update the dac outputs directly, independent of the state of the ldac pin. i 2 c slave address the ad5696 / ad5694 ha ve a 7 - bit i 2 c slave address. the five msbs are 00011 , and the two lsbs (a1 and a0) are set by the state of the a 1 and a 0 address pin s . the ability to make hard - wired changes to a 1 and a 0 allows the user to incorporate up to four ad5696 / ad5694 devices on one bus ( see table 10). table 10 . device address selection a 1 pin connection a 0 pin connection a 1 bit a 0 bit gnd gnd 0 0 gnd v logic 0 1 v logic gnd 1 0 v logic v logic 1 1 serial operation the 2 - wire i 2 c serial bu s protocol operates as follows: 1. the master initiates a data transfer by establishing a start condition when a high - to - low transition on the sda line occurs while scl is high. the following byte is the address byte, which c onsi sts of the 7 - bit slave address. 2. the slave device with the transmitted address responds by pulling sda low during the 9 th clock pulse (this is called the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its input shi ft register. 3. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). t ransitions on the sda line must occur during the low period of scl ; sda must remain stable during the high period of scl. 4. after all data bits are read or written, a stop condition is established. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition. in r ead mode, the master issues a no acknowledge for the 9 th clock pulse (th at is, th e sda line remains high). the master then brings the sda line low before the 10 th clock pulse and then high again during the 10 th clock pulse to establish a stop condition. write operation when writing to the ad5696 / ad5694 , the user must begin with a start command followed by an address byte (r/ w = 0), after which the d ac acknowledges that it is prepared to receive data by pulling sda low. the ad5696 / ad5694 require two bytes of data for the dac and a command byte that controls vario us dac functions. three bytes of data must , therefore , be written to the dac with the command byte followed by the most significant data byte and the least significant data byte, as shown in figure 37 . all these data bytes are acknowledged by the ad5696 / ad5694 . a stop condition follows. figure 37 . i 2 c write operation frame 2 command byte frame 1 slave address 1 9 9 1 scl start by master ack by ad5696/ad5694 ack by ad5696/ad5694 sda r/w db23 a0 a1 1 0 0 0 1 db22 db21 db20 db19 db18 db17 db16 1 9 9 1 ack by ad5696/ad5694 ack by ad5696/ad5694 frame 4 least significant data byte frame 3 most significant data byte stop by master scl (continued) sda (continued) db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 10799-303
data sheet ad5696/ad5694 rev. a | page 19 of 24 r ead o peration when reading data back from the ad5696 / ad5694 , the user must begin with a start command followed by an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. th e address byte m ust be followed by the co mmand byte , which determines both the read command that is to follow and the pointer address to read from ; the command byte is also acknowledged by the dac. the user configures the channel to read back the contents of one or more d ac registers and sets the readback command to active using the co mmand byte. following this, the master establishes a repeated start condition , and the address is resent with r/ w = 1. this byte is acknowledged by the dac , indicating that it is prepared to transmit data. two bytes of data are then read fro m the dac, as shown in figure 38 . a nack condition from the master , followed by a stop condition , completes the read sequence. i f more than one dac is selected , channel a is read back by default . m ultiple dac readback sequence when reading data back from multiple ad5696 / ad5694 dacs, the user begins with an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. th e address byte must be followed by the co mm and byte, which is also acknowledged by the dac. the user selects the first channel to read back using the command byte. following this, the master establishes a repeated start condition, and the address is resent with r/ w = 1. this byte is acknowledged by the dac , indicating that it is prepared to transmit data. the first two bytes of data are then read from dac input register n ( select ed using the co mmand byte ) , most significant byte first , as shown in figure 38 . the next two bytes read back are the contents of dac input register n + 1 , and the next bytes read back are the contents of dac input register n + 2. data is read from the dac input registers in this auto - increment ed fashion until a nack followed by a stop condition follows. if the contents of dac input register d are read out , the next two bytes of data that are read are the contents of dac input register a. figure 38 . i 2 c read operation frame 2 command byte frame 1 slave address 1 1 0 0 0 1 a1 a0 r/w db23 db22 db21 db20 db19 db18 db17 db16 9 9 1 start by master ack by ad5696/ad5694 ack by ad5696/ad5694 scl scl sda 1 9 9 1 1 9 9 1 ack by ad5696/ad5694 repeated start by master ack by master frame 4 most significant data byte n frame 3 slave address ack by master nack by master stop by master frame 6 most significant data byte n + 1 frame 5 least significant data byte n 1 0 0 0 1 a1 a0 r/w db15 db14 db13 db12 db11 db10 db9 db8 sda scl (continued) sda (continued) db7 db6 db5 db4 db3 db2 db1 db0 db15 db14 db13 db12 db11 db10 db9 db8 10799-304
ad5696/ad5694 data sheet rev. a | page 20 of 24 power - down operation command 0100 is designated for the power - down function. the ad5696 / ad5694 provide three separate power - down modes (see table 11). thes e power - down modes are software program - mable by setting bit db7 to bit db0 in the input shift register (see table 12) . two bits are associated with each dac channel. table 11 shows how the state of the se two bits corresponds to the mode of oper a tion of the device. table 11 . modes of operation operating mode pdx1 pdx0 normal operation 0 0 power - down modes 1 k ? to gnd 0 1 100 k ? to gnd 1 0 three - state 1 1 any or all dacs (dac a to dac d ) can be powered down to the selected mode by setting th e corresponding bits in the input shift register . see table 12 for the contents of the input shift register during the power - down/power - up operation. when both bit pd x 1 and bit pd x 0 (where x is the dac selected) in the input shift register are set to 0, the part s work normally with their normal power consumption of 0.59 m a a t 5 v. when bit pdx1, bit pdx0, or both bit pdx1 and bit pdx0 are set to 1, the part is in power - down mode. in power - down mode, the supply current falls to 4 a a t 5 v. in power - down mode, the output stage is internally switched from the output of the amplifier to a resistor network of known values. in this way, the output impedance of the part is known wh en the part is in power - down mode. table 11 lists the three power - down options. the output is connected internally to gnd through either a 1 k? or a 100 k? resistor, or it is left open - circuited (three - state). the output stage is i llustrated in figure 39. figure 39 . output stage during power - down the bias generator, output amplifier, resistor string, and other associated linear circuitry are shut down when power - down mode is activated. however, the contents of the dac register s are unaffected in power - down mode , and t he dac register s can be updated while the device is in power - down mode. the time required to exit power - down is typically 2 .5 s for v dd = 5 v . load dac (hardware ldac pin) the ad5696 / ad5694 dacs have double buffered interfa ces consisting of two banks of registers: input registers and dac registers. the user can write to any combination of the input registers (see table 9 ). updates to the dac registers are con - trolled by the ldac pin. figure 40 . simplified diagram of input loading circuitry for a single dac table 12 . 24- bit input shift register contents for power - down/power- up operation 1 db23 ( m sb) db22 db21 db20 db19 to db16 db15 to db8 db7 db6 db5 db4 db3 db2 db1 db0 (lsb) 0 1 0 0 x x pdd1 pdd0 pdc1 pdc0 pdb1 pdb0 pda1 pda0 command bits (c3 to c0) address bits (d ont care ) dont care power -d own s elect , dac d power -d own s elect , dac c power -d own s elect , dac b power -d own s elect , dac a 1 x = dont care. resistor network v out x dac power-down circuitry amplifier 10799-058 sda scl v out x dac register input shift register output amplifier ldac v ref input register 12-/16-bit dac 10799-059
data sheet ad5696/ad5694 rev. a | page 2 1 of 24 instantaneous dac updating ( ldac held low ) for instantaneous updating of the dacs, ldac is held low while data is clocked into the inpu t register using command 0001 . both t he addressed input register and the dac register are updated on the 24 th clock , and the output begins to change (see table 14). deferred dac updating ( ldac pulsed low ) for deferred updating of the dacs, ldac is held high while data is clocked into the input register usin g command 0001 . all dac outputs are asynchronously updated by pull ing ldac low after the 24 th clock . the update occurs on the falling edge of ldac . ldac mask register command 0101 is reserved for the software ldac function. when this command is executed, the address bits are ignored. when writing to the dac using command 0101, the 4 - bit ldac mask register (db3 to db0) is loaded. bit d b3 of the ldac mask register corresponds to dac d; bit db2 corresponds to dac c; bit db1 corresponds to dac b; and bit db0 corresponds to dac a. the default value of these bits is 0; that is, the ldac pin works normally. setting any of these bits to 1 forces th e selected dac channel to ignore transitions on the ldac pin, regardless of the state of the hardware ldac pin . this flexibility is use ful in appli - cation s where the user wishes to select which channels respond to the ldac pin . the ldac mask register allow s the user extra flexibility and control over the hardware ldac pin (see table 13 ). setting the ldac bit (db3 to db0) to 0 for a dac channel allows the hard - ware ldac pin to control the updating of that channe l. table 13. ldac overwrite definition load ldac register ldac bit (db3 to db0) ldac pin ldac operation 0 1 or 0 determined by the ldac pin. 1 x 1 dac channels are update d . ( dac channels see ldac pin as 1 . ) 1 x = dont care. hardware reset pin ( reset ) reset is an active low reset that allows the outputs to be cleared to either zero scale or midscale. the clear code value is user select - able via the reset select pin (rstsel). it is necessary to keep reset low for a minimum of 30 ns to comple te th e operation. when the reset signal is returned high, the output remains at the cleared value until a new value is programmed. the outputs cannot be updated with a new value while the reset pin is low. there is also a software executable reset function that resets the dac to the power - on reset code. command 0110 is designated for this software reset function (see table 8 ). any events on ldac or reset during power - on reset are ignored. reset select pin (rs tsel) the ad5696 / ad5694 contain a power - on reset circuit that controls the output voltage during power - up. when the rstsel pin is tied to gnd, the output s power up to zero scale (note that this is outside the linear region of the dac). when the rstsel pin is tied to v dd , the out put s power up to midscale. the output s remain powered up at the level set by the rstsel pin until a valid write sequence is made to the dac. table 14. write commands and ldac pin truth table 1 command description hardware ldac pin state input register contents dac register contents 0001 write to input register n ( d ependent on ldac ) v logic data u pdate no change (no update) gnd 2 data u pdate data u pdate 0010 update dac register n with contents of input register n v logic no c hange updated with i nput register contents gnd no c hange updated with i nput register contents 0011 write to and update dac channel n v logic data u pdate data u pdate gnd data u pdate data u pdate 1 a high to low transition on the hardware ldac pin always updates the conten ts of the dac register with the contents of the input register on channels that are not masked (blocked) by the ldac mask register. 2 when the ldac pin is permanently tied low, the ldac mask bits are ig nored.
ad5696/ad5694 data sheet rev. a | page 22 of 24 applications informa tion microprocessor inter facing microprocessor interfacing to the ad5696 / ad5694 is via a serial bus that uses a standard protocol that is compatible with dsp proces sors and microcontrollers. the com munications channel req uires a 2 - wire interfa ce consisting of a clock signal and a data signal. ad5696 / ad5694 to adsp - bf531 interface the i 2 c interface of the ad5696 / ad5694 is designed for eas y connect ion to industry - standard dsps and microcontrollers. figure 41 shows the ad5696 / ad5694 connect ed to the analog devices , inc., blackfin? processor . the blackfin processor has an integrated i 2 c port that can be connected directly to the i 2 c pins of the ad5696 / ad5694 . figure 41 . ad5696 / ad5694 to adsp - bf531 interface layout guidelines in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the pcb on which the ad5696 / ad5694 are mounted should be designed so that the ad5696 / ad5694 lie on the analog plane. the ad5696 / ad5694 should ha ve ample supply bypassing of 10 f in parallel with 0.1 f on each supply , located as close to the package as possible, ideally right up against the dev ice. the 10 f capacitor i s the tantalum bead type. the 0.1 f capacitor should have low effective serie s resistance (esr) and low effective series inductance (esi) , such as the common ceramic types ; these capacitors provide a low impedance path to ground at high frequencies to handle transient currents d ue to internal logic switching. in systems where many devices are on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate e asily. the ad5696 / ad5694 lfcsp models have an exposed pad beneath the device. connect this pad to the gnd supply for the part. for optimum performance, use special considerations to design the motherboard and to mount the package. for enhanced thermal, electrical, and board level performance, solder the exposed pad on the bottom of the lfcsp package to the corresponding thermal land paddle on the pcb. design thermal vias into the pcb land paddle area to fu rther improve heat dissipation. the gnd plane on the device can b e increased (as shown in figure 42 ) to provide a natural heat sinking effect. figure 42 . paddle connection to board galvanically isolate d interface in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common - mode voltages that may occur. the analog devices i couple r? products provide voltage iso - lation in excess of 2 .5 kv. the serial loading struc ture of the ad5696 / ad5694 makes the part ideal for isolated interfaces because the number of interface lines is kept to a minimum. figure 43 shows a 4 - channel isolated interface to the ad5696 / ad5694 using the adum1400 . for more information, visit http://www.analog.com/icouplers . figure 43 . isolated interface adsp-bf531 scl gpio1 sda gpio2 ldac pf9 reset pf8 ad5696/ ad5694 10799-164 ad5696/ ad5694 gnd plane board 10799-166 encode serial clock in controller adum1400 serial data out reset out load dac out decode to scl to sda to reset to ldac v ia v oa encode decode v ib v ob encode decode v ic v oc encode decode v id v od 10799-167
data sheet ad5696/ad5694 rev. a | page 23 of 24 outline dimensions figure 44 . 16 - lead lead frame chip scale package [lfcsp _wq ] 3 mm 3 mm body, very very thin quad (cp - 16 - 22 ) dimensions shown in millimeters figure 45 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters 3.10 3.00 sq 2.90 0.30 0.23 0.18 1.75 1.60 sq 1.45 08-16-2010-e 1 0.50 bsc bot t om view top view 16 5 8 9 12 13 4 exposed pa d pin 1 indic a t or 0.50 0.40 0.30 sea ting plane 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.80 0.75 0.70 compliant to jedec standards mo-220-weed-6. 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab
ad5696/ad5694 data sheet rev. a | page 24 of 24 ordering guide model 1 resolution temperature range accuracy (inl) package description package option branding ad5696acpz -rl7 16 bits ?40c to +105c 8 lsb 16 - lead lfcsp_wq cp -16 -22 dj8 ad5696bcpz -rl7 16 bits ?40c to +105c 2 lsb 16 - lead lfcsp_wq cp -16 -22 dj 9 ad5696 aruz 16 bits ?40c to +105c 8 lsb 16 - lead tssop ru -16 ad5696 aruz -rl7 16 bits ?40c to +105c 8 lsb 16 - lead tssop ru -16 ad5696 bruz 16 bits ?40c to +105c 2 lsb 16 - lead tssop ru -16 ad5696 bruz -rl7 16 bits ?40c to +105c 2 lsb 16 - lead tssop ru -16 ad5694bcpz -rl7 12 bits ?40c to +105c 1 lsb 16 - lead lfcsp_wq cp -16 -22 dj q ad5694 aruz 12 bits ?40c to +105c 2 lsb 16 - lead tssop ru -16 ad5694 aruz -rl7 12 bits ?40c to +105c 2 lsb 16 - lead tssop ru -16 ad5694 bruz 12 bits ?40c to +105c 1 lsb 16 - lead tssop ru -16 ad5694 bruz -rl7 12 bits ?40c to +105c 1 lsb 16 - lead tssop ru -16 eval - ad5696rsdz ad5696 tssop evaluation board eval - AD5694Rsdz ad5694 tssop evaluation board 1 z = rohs compliant part. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2012 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10799 - 0 - 6/13(a)

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